Section 1: The Logical Bedrock (Questions 1–10)Focus: Boolean Algebra, Gates, and CMOS Physics Before an interviewer asks about your experience with UVM or Synthesis, they will test your "gate-level intuition." In 2026, understanding the physical limitations of gates (like leakage and noise margins) is what separates a technician from an engineer.
Universality: Why are NAND and NOR gates called "Universal"? Implement a 3-input OR gate using only 2-input NAND gates.
De Morgan’s in Practice: How do De Morgan’s Laws help in reducing the area of a physical layout?
The CMOS Inverter: Sketch the VTC (Voltage Transfer Characteristic). If the PMOS is significantly weaker than the NMOS, how does the switching threshold $V_m$ shift?
Power Dynamics: Write the equation for total power dissipation in a CMOS circuit.$$P_{total} = \alpha C V_{dd}^2 f + I_{sc} V_{dd} + I_{leakage} V_{dd}$$
Fan-out Constraints: What physical factors limit the fan-out of a logic gate in a high-speed design?Transmission Gates: Explain why a TG is preferred over a simple NMOS pass transistor for passing a "strong 1.
"Noise Margins: Define $NM_H$ and $NM_L$. Why is a high noise margin critical in sub-1V designs?
Gray Code: Why is it mathematically safer to use Gray code for pointers in Asynchronous FIFOs?Don’t Cares: How can "Don’t Care" conditions in a K-Map be used to optimize power, not just area?
Schmitt Trigger: What is hysteresis, and how does a Schmitt trigger handle noisy input signals?Collaborator’s Corner: "When I interview candidates, I often ask Question 4. Most know the formula, but the best candidates can explain why leakage power ($I_{leakage}$) is becoming the dominant factor as we shrink below 5nm.
"Section 2: Combinational Mastery & Arithmetic (Questions 11–20)Focus: Multiplexers, Adders, and Data Paths
The Mux-Logic Challenge: Implement a 2-input XOR gate using only one 2:1 Multiplexer and an inverter.
Decoder Expansion: How do you build a 4:16 decoder using only 2:4 decoders?Look-ahead vs. Ripple: In terms of $O(n)$ complexity, compare the delay of a Ripple Carry Adder (RCA) and a Carry Look-ahead Adder (CLA).Priority Encoders: Explain the logic behind a priority encoder. What happens if all inputs are zero?
Barrel Shifters: Why is a Barrel Shifter used in CPUs instead of a standard shift register for N-bit shifts?
Magnitude Comparators: Design a 2-bit comparator using basic gates.
Booth’s Algorithm: How does Booth’s encoding reduce the number of partial products in multiplication?
The Full Adder: Implement a Full Adder using only two 4:1 Multiplexers.
Parity Generators: Explain the difference between even and odd parity and their role in error detection.
Static Hazards: Identify a potential hazard in a logic circuit and explain how adding "redundant" gates eliminates it
.Section 3: Sequential Logic & The Sync Problem (Questions 21–35)Focus: Latches, Flip-Flops, and FSMs
This is the most common failure point for candidates. You must master the transition from "combinational" (stateless) to "sequential" (stateful) logic.
Latch vs. Flip-Flop: This is the "Golden Question." Compare level-triggering vs. edge-triggering.
Metastability: What is the physical state of a flip-flop during metastability? How do you calculate MTBF?
Setup and Hold Definitions: Define $T_{setup}$ and $T_{hold}$ without using a textbook definition. Explain them in terms of data stability
.Synchronizers: Draw a 2-flop synchronizer. Why doesn't a single flip-flop work for Clock Domain Crossing (CDC)?
The Master-Slave DFF: Explain how the Master-Slave configuration prevents the "Race Around" condition.
Mealy vs. Moore: Which FSM model is more likely to have "glitchy" outputs, and why?
State Encoding: When would you choose One-Hot encoding over Binary/Gray encoding?
Divide-by-N Counters: Design a divide-by-3 counter with a 50% duty cycle
.Johnson Counter: What are the advantages of a Johnson counter over a Ring counter?Self-Correction: How do you design an FSM that can recover from an illegal state?
Clock Gating: Draw an Integrated Clock Gating (ICG) cell. Why is a simple AND gate insufficient for clock gating?
Pulse Width: What is the minimum clock pulse width required for a flip-flop to function correctly?LFSRs: What is a Linear Feedback Shift Register, and how is it used in Built-In Self-Test (BIST)?Setup-Hold Trade-offs: Can you increase the clock frequency to fix a hold violation? (Answer: No).The Reset Strategy: Compare Synchronous vs. Asynchronous Reset. Which is safer for high-speed designs?Section 4: Static Timing Analysis (STA) (Questions 36–45)
Focus: The "Math" of Silicon Success In modern VLSI, the "Design" is only 30% of the work; the rest is "Timing Closure." Use these equations to prove your technical depth.
The Setup Constraint: Write the equation for the maximum frequency of a circuit:$$T_{clk} \geq T_{cq} + T_{comb} + T_{su} - T_{skew}
The Hold Constraint: Explain why the clock period $T_{clk}$ is absent from the hold equation:$$T_{cq} + T_{comb} \geq T_{h} + T_{skew}
Clock Skew vs. Jitter: Define both. How does "uncertainty" affect your timing margins?False Paths: Give a real-world example of a false path (e.g., a path between a configuration register and a stable logic block).Multi-cycle Paths: How do you specify a path that requires 2 clock cycles to settle in an SDC (Synopsys Design Constraints) file?
Time Borrowing: How do transparent latches allow a designer to "borrow" time from a previous cycle?PVT Corners: What are Process, Voltage, and Temperature corners? Why do we check timing at "Best Case" and "Worst Case"?
Recovery and Removal: Why are these terms used instead of Setup and Hold for asynchronous signals?The Impact of Buffers: How does adding a buffer affect Setup time vs. Hold time?
Critical Path Analysis: If your design fails Setup by 50ps, what are the three steps you take to fix it?Section 5: The 2026 Horizon (Questions 46–50)Focus: Emerging Technologies
Backside Power Delivery: How does separating the power delivery network from the signal routing network reduce IR drop?
GAAFET Architecture: How does the "Gate-All-Around" structure improve electrostatic control compared to FinFETs?
Dark Silicon: In a multi-core processor, why can't all cores run at maximum frequency simultaneously?
Chiplet Interconnects: What are the challenges of "Die-to-Die" (D2D) communication in terms of latency and power?
AI in EDA: How is Reinforcement Learning being used to automate the floorplanning of digital chips?