ASIC Engineer, Design (Freshers)

Candidates typically face a three‑stage process: an online aptitude test lasting 30‑40 minutes, followed by a technical interview that probes RTL coding, verification strategies, and basic VLSI concepts. The final HR round assesses cultural fit and communication skills. The overall difficulty is moderate; thorough preparation on digital design fundamentals and practice of coding problems greatly improves success chances.

Metacareers.com promotes a collaborative and inclusive work culture where fresh engineers are mentored by industry veterans. Employees enjoy flexible working hours, regular knowledge‑sharing sessions, and a strong emphasis on work‑life balance, making it an ideal environment for early‑career growth.

B.Tech or M.Tech in VLSI, Electronics & Communication, Electrical Engineering, Computer Engineering or related streams; Minimum 60% aggregate (or CGPA 6.5/10); Batch year 2025 (or 2026); No active backlogs at the time of joining; Strong academic record in digital design, computer architecture, or related subjects.

Round 1: Online Aptitude Test → Round 2: Technical Interview (Design, Verification & Coding) → Round 3: HR Interview

Metacareers.com is one of India’s fastest‑growing job portals dedicated to fresh talent. Since its inception, the platform has built a strong ecosystem connecting engineering graduates with leading technology firms across the country. With a focus on transparent hiring, career guidance, and skill‑upskilling, Metacareers.com has earned a reputation for being a reliable launchpad for freshers seeking high‑impact roles in cutting‑edge domains. The company’s culture emphasizes continuous learning, mentorship, and a collaborative environment that encourages young engineers to experiment, fail fast, and innovate. The role of ASIC Engineer – Design is tailored for recent graduates who are passionate about digital chip design and want to dive deep into the end‑to‑end ASIC development flow. As a junior designer, you will work under seasoned architects, contribute to micro‑architecture discussions, and translate specifications into synthesizable RTL or High‑Level Synthesis (HLS) code. You will also be involved in verification infrastructure development, performance‑power‑area (PPA) analysis, and post‑silicon validation, gaining exposure to the complete lifecycle of a silicon product. Key Responsibilities: 1. Participate actively in micro‑architecture, design, and verification review meetings and provide constructive feedback. 2. Write, simulate, and verify RTL or HLS code for assigned IP blocks. 3. Perform static timing analysis and power estimation to meet PPA targets. 4. Develop and maintain verification testbenches, UVM environments, and coverage models. 5. Collaborate with physical design teams to ensure area and routing constraints are met. 6. Support simulation accelerators and assist in post‑silicon bring‑up activities. 7. Debug design issues using waveform analysis and formal verification tools. 8. Document design specifications, test plans, and validation results. 9. Stay updated with the latest ASIC design methodologies and industry standards. 10. Contribute ideas for process improvements and automation scripts. Tech Stack: Verilog/SystemVerilog, VHDL, C/C++, High‑Level Synthesis (C++/SystemC), Synopsys Design Compiler, Cadence Innovus, Mentor Graphics Questa, Python for scripting, Linux, Git. Growth Path: Junior ASIC Designer → ASIC Design Engineer → Senior ASIC Engineer → Lead Design Engineer → ASIC Architecture Lead. The role offers mentorship, regular technical workshops, and the chance to work on high‑volume consumer and automotive silicon projects. Why Join Metacareers.com: Apart from a competitive 12 LPA package, you will be part of a vibrant community that values learning and innovation. The company provides access to premium training resources, a clear career progression roadmap, and a supportive work‑life balance that encourages personal growth alongside professional excellence.