DFT Engineer – Design for Testability

Round 1: Online aptitude test → Round 2: Technical interview (DFT concepts, coding, problem solving) → Round 3: HR interview (fitment, communication, expectations)

Docs.google.com (Google) is renowned for its open, innovative culture where engineers are encouraged to experiment and share ideas freely. Employees enjoy generous learning budgets, flexible work arrangements, and a strong emphasis on work‑life balance, making it a top choice for fresh talent seeking growth.

The typical interview at docs.google.com consists of an online coding assessment followed by two technical rounds focusing on data structures, algorithms, and domain‑specific knowledge, and finally an HR round to assess cultural fit. The difficulty is moderate to high, with emphasis on problem‑solving speed and clear communication. Candidates are advised to practice coding on platforms, review system design basics, and be ready to discuss past projects confidently.

B.Tech/M.Tech in VLSI, Electronics & Communication, Electrical Engineering, Computer Science or related branches; Minimum 60% aggregate (or CGPA 6.5/10); Final year students or fresh graduates of 2024‑2025 batches; No active backlogs at the time of joining; Strong academic record in digital design, computer architecture, or related subjects.

Auxera Global Tech Pvt. Ltd. is an emerging player in the semiconductor and ASIC domain, headquartered in India with a vision to deliver cutting‑edge silicon solutions for global customers. The company focuses on end‑to‑end ASIC development, covering front‑end design, design‑for‑testability (DFT), physical design, and embedded firmware. With a strong R&D culture, Auxera collaborates with leading fab houses and IP vendors, enabling fresh talent to work on real‑world silicon projects that power consumer electronics, automotive, and IoT devices. The firm prides itself on a merit‑based growth environment, encouraging engineers to experiment, learn, and contribute to high‑impact products. The DFT Engineer role is tailored for fresh graduates who are eager to dive into the world of ASIC testing and validation. As a DFT Engineer, you will be part of a multidisciplinary team that designs test structures, develops scan insertion strategies, and creates built‑in self‑test (BIST) solutions to ensure silicon quality and yield. You will get hands‑on exposure to industry‑standard EDA tools, work closely with physical design and verification engineers, and contribute to the creation of test plans that meet stringent customer specifications. Key Responsibilities: 1. Develop and integrate scan chains, built‑in self‑test (BIST) and boundary‑scan architectures into ASIC designs. 2. Write and verify DFT scripts using TCL, Python, or Perl for automation of test insertion. 3. Collaborate with RTL designers to insert test points and ensure DFT compliance. 4. Perform fault simulation and coverage analysis using tools like Synopsys TetraMAX or Mentor Tessent. 5. Generate test patterns and work with test engineers to validate silicon prototypes. 6. Participate in design reviews, providing DFT feedback and suggesting improvements. 7. Document DFT methodology, test plans, and coverage reports for internal and customer audits. 8. Stay updated with the latest DFT standards (IEEE 1149.1, 1500) and industry best practices. 9. Assist in debugging test failures and root‑cause analysis on silicon. 10. Contribute to continuous improvement initiatives within the DFT team. Tech Stack: Synopsys TetraMAX, Mentor Tessent, Cadence Encounter, TCL, Python, Perl, Verilog/SystemVerilog, Linux environment, Git. Growth Path: Starting as a Junior DFT Engineer, you can progress to Senior DFT Engineer, DFT Lead, and eventually to ASIC Design Manager or ASIC Verification Lead, depending on performance and interest. The company also offers cross‑training opportunities in physical design and embedded firmware, allowing a holistic ASIC career. Why Join Auxera? The firm offers a vibrant startup‑like atmosphere with the stability of an established tech company. Freshers get to work on real ASIC projects from day one, receive mentorship from seasoned VLSI professionals, and benefit from a performance‑driven compensation package. The exposure to end‑to‑end ASIC flow, coupled with opportunities for international collaboration, makes Auxera an ideal launchpad for a long‑term career in the semiconductor industry.